Recently, miniaturization of a wiring has progressed along with miniaturization of semiconductor devices. As a result, a problem in which RC delay caused by an increase in wiring resistance and an increase in coupling capacitance between wirings obstructs a high-speed operation of a device has become obvious. For this reason, copper (Cu), which has a bulk resistance lower than that of aluminum (Al) or tungsten (W), which has conventionally been used as a wiring material, has been used recently, and a low dielectric constant film (Low-k film) has been used as an interlayer insulating film.
However, as the miniaturization progresses further, new problems are emerging in a Cu wiring. That is, according to the ITRS roadmap, a wiring width used in a device of the 14-nm generation is 32 nm. This is narrower than about 39 nm, which is the mean free path of electrons in a Cu material, causing an increase in resistance value due to scattering. Specifically, the resistance value of a wiring is expressed as the sum of the resistance value of a bulk, a resistance factor by surface scattering, and a resistance factor by grain boundary scattering. Since both the resistance factor by surface scattering and the resistance factor by grain boundary scattering are proportional to the mean free path, when the mean free path of electrons becomes larger than the wiring width, collision of electrons with a wiring side surface or a grain boundary becomes dominant, causing an increase in resistance value due to scattering. This becomes more evident as the wiring becomes finer.
Therefore, as a wiring material, researches have been made on ruthenium (Ru), of which the bulk resistance value is not as low as Cu, but the mean free path of electrons in the material is shorter than that of Cu. Specifically, the bulk resistance value of Ru is 7.1 μΩ-cm, which is higher than 1.7 μΩ-cm of Cu, but the mean free path of electrons therein is 10.8 nm, which is shorter than 38.7 nm in Cu.
In addition, since the melting point of Ru is 2334° C. and is higher than 1085° C., which is the melting point of Cu, Ru is more advantageous than Cu from the viewpoint of electromigration resistance.
Therefore, a technology to form a Ru wiring by embedding a Ru film in a trench by atomic layer deposition (ALD) has been proposed (see, e.g., L. G. Wen et al., Proceeding of IEEE IITC/AMC 2016, pp 34-36). In addition, formation of a Ru film by chemical vapor deposition (CVD) has been performed (see, e.g., Japanese Laid-Open Patent Publication No. 2010-212601).
Meanwhile, as a technology to form a Cu wiring, there has been known a technology in which, after a barrier film is formed on an interlayer insulating film having a trench formed in a semiconductor wafer surface, a Cu film is embedded in the trench, and is then flattened by chemical mechanical polishing (CMP) (see, e.g., Japanese Laid-Open Patent Publication No. 2006-148075). Therefore, even when forming a Ru wiring, it is conceivable to form a Ru film by ALD or CVD and to flatten the Ru film by a CMP treatment.